1. Field of the Invention
The present invention relates to a program controlled processor for use where high speed operating performance is required, and in detail to the architecture of a digital signal processor (DSP) used in digital signal processing applications.
2. Description of the Prior Art
An instruction set of a prior art program controlled processor such as a microprocessor includes ordinary instructions such as operations, reading and writing to and from a memory or register and branching. A program using these instructions can implement various processings by executing these instructions sequentially one at a time.
In dynamic image processing and other digital signal processing applications requiring high speed operating performance, however, improving the processing performance of a program controlled digital signal processor (DSP) has been an obstacle to be solved.
For example, Japanese laid-open Patent Publication No. 61,901/1993 has proposed a method to solve this problem. This method provides a pipeline operator as an operating resource of a processor, and includes vector processing instructions in the instruction set.
Demand for higher resolution dynamic image processing is growing, however, and further improvement of processor performance is now a problem. More specifically, in high resolution dynamic image processing applications requiring high speed processing of large amounts of data, the architectures of prior art program controlled processors offer insufficient processing performance, and improving data processing performance is the single biggest problem.